Process for making a silicon-on-insulator ledge and structures achieved thereby

ABSTRACT

A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

[0001] This application is a Continuation of U.S. application Ser. No.10/118,569, filed Apr. 8, 2002, which is incorporated herein byreference.

FIELD OF THE INVENTION

[0002] An embodiment relates to semiconductor processing. One embodimentin particular relates to a process for making a silicon-on-insulatorledge structure that includes a partially isolated active area in asemiconductive substrate.

BACKGROUND

[0003] Semiconductor processing is an intensive activity during whichseveral processes are integrated to achieve a working device.Miniaturization is the process of crowding more semiconductive devicesonto a smaller substrate area in order to achieve better device speed,lower energy usage, and better device portability, among others. Newprocessing methods must often be developed to enable miniaturization tobe realized. Preferably, the processing methods needed to fabricate suchdevices are developed in a manner that existing processing equipment canbe used.

[0004] The pressure to continue the miniaturization process also leadsto new semiconductor device structures. As individual active devicesbecome smaller and are fabricated closer together, leakage and secondorder effects become more significant. In the field of metal oxidesemiconductor field-effect transistors (MOSFET), device leakage andminiaturization appear to be antagonistic challenges. Often, oxidationis carried out for the purpose of isolation, but oxidation often impartsstresses in the workpieces that lead to device failure. Depositionprocesses, although necessary, are time-consuming and costly. Further,deposition processes require masking and careful application. Further,deposition processes are preferentially applied when an integratedprocess can take advantage of a given deposition simultaneously inunrelated areas of a device.

SUMMARY

[0005] The above mentioned problems and challenges are overcome byembodiments of this invention. One embodiment is directed to a processof forming a partially isolated structure of sufficient size to permitthe fabrication of an active device thereon. The process includesforming an etch-selective region in the semiconductive workpiece thatrestricts the effects of an isotropic etch. The etch-selective region iscreated by implantation that causes the semiconductive material tobecome amorphous.

[0006] Protective material, such as a polysilicon layer and a nitridelayer, is deposited over a pad oxide layer to protect the pad oxidelayer. An active area is defined by patterning a mask. The protectivematerial, the pad oxide layer, and finally the substrate are etched toform a trench around the active area. A protective film that istypically nitride material, is formed upon exposed silicon. Thesubstrate is etched to deepen the trench around what will become theactive area to a level below the protective layer. The etch-selectiveimplantation region is either then formed or exposed by the previousetch. An isotropic etch follows that acts to substantially insulate theactive area by its undercutting effect. The implantation region isannealed to repair the crystal lattice of the substrate. Thereafter, analternative oxidation process is done to further isolate the active areafrom adjacent active areas or other structures. Oxide spacers are formedon the sides of the active area, and the remainder of the trench isfilled to form a shallow trench isolation (STI) structure.

[0007] An embodiment is also directed to a partially isolated structureof sufficient size to permit the fabrication of an active devicethereon. The partially isolated structure is comprised of a portion ofthe a substrate that has an undercut lateral cavity that is shaped in amanner which defines the active area of the partially isolatedstructure.

[0008] The process and structure of various embodiments enable activedevices to be packed into ultra-dense configurations using currentlyavailable fabrication equipment. Because the diode junctions of activedevices are formed in areas of the substrate that are at least partiallyisolated from the remainder of the substrate, the diode junctions may befabricated to be less leaky.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order that the manner in which embodiments of the presentinvention are obtained, a more particular description of the inventionbriefly described above will be rendered by reference to specificembodiments thereof which are illustrated in the appended drawings.Understanding that these drawings depict only typical embodiments of theinvention that are not necessarily drawn to scale and are not thereforeto be considered to be limiting of its scope, the invention will bedescribed and explained with additional specificity and detail throughthe use of the accompanying drawings in which:

[0010]FIG. 1 is a cross section of a structure during processingaccording to an embodiment.

[0011]FIG. 2 is a cross section of the structure depicted in FIG. 1after further processing.

[0012]FIG. 3 is a cross section of the structure depicted in FIG. 2after further processing in which a nitride film has been grown onexposed silicon.

[0013]FIG. 4 is a cross section of the structure depicted in FIG. 3after further processing.

[0014]FIG. 5 is a cross section of the structure depicted in FIG. 4after further processing in which a lateral recess has been etched.

[0015]FIG. 6 is a cross section of the structure depicted in FIG. 5after further processing.

[0016]FIG. 7 is a cross section of the structure depicted in FIG. 6after further processing in which oxidation and oxide fill processeshave been done.

[0017]FIG. 8 is a cross section of the structure depicted in FIG. 6after alternative further processing in which minimal oxidation or nooxidation, and oxide fill processes have been done.

[0018]FIG. 9 is a cross section of the structure depicted in FIG. 6after alternative further processing in which minimal oxidation or nooxidation, and oxide fill processes have been done.

[0019]FIG. 10 is a cross section that includes the structure depicted inFIG. 9 after further processing.

[0020]FIG. 11 is a cross section that includes a portion of thestructure depicted in FIG. 10 after further processing.

[0021]FIG. 12 is a cross section of a structure during processingaccording to an embodiment.

[0022]FIG. 13 is a cross section of the structure depicted in FIG. 12after an anisotropic etch.

[0023]FIG. 14 is a cross section of the structure depicted in FIG. 13after further processing in which a nitride film has been grown onexposed silicon.

[0024]FIG. 15 is a cross section of the structure depicted in FIG. 14after further processing.

[0025]FIG. 16 is a cross section of the structure depicted in FIG. 15after further processing in which a lateral recess has been etched.

[0026]FIG. 17 is a cross section of the structure depicted in FIG. 16after an anneal process.

[0027]FIG. 18 is a cross section of a structure during processingaccording to an embodiment.

[0028]FIG. 19 is a cross section of the structure depicted in FIG. 18after an anisotropic etch.

[0029]FIG. 20 is a cross section of the structure depicted in FIG. 19after further processing in which a nitride film has been grown onexposed silicon.

[0030]FIG. 21 is a cross section of the structure depicted in FIG. 20after further processing.

[0031]FIG. 22 is a cross section of the structure depicted in FIG. 21after further processing in which a lateral recess has been etched.

[0032]FIG. 23 is a cross section of the structure depicted in FIG. 22after an anneal process.

[0033]FIG. 24 is a top view of a wafer or substrate containingsemiconductor dies in accordance with an embodiment.

[0034]FIG. 25 is a block diagram of a circuit module in accordance withan embodiment.

[0035]FIG. 26 is a block diagram of a memory module in accordance withan embodiment.

[0036]FIG. 27 is a block diagram of an electronic system in accordancewith another embodiment the present invention.

[0037]FIG. 28 is a block diagram of a memory system in accordance withan embodiment.

[0038]FIG. 29 is a block diagram of a computer system in accordance withan embodiment.

DETAILED DESCRIPTION

[0039] In one embodiment as depicted in FIG. 1, a substrate 10 isprovided which includes a semiconductive material. The terms wafer andsubstrate used in the following description include any structure havingan exposed surface with which to form the integrated circuit (IC)structure relating to embodiments of the invention. The term substrateis understood to include semiconductor wafers. The term substrate isalso used to refer to semiconductor structures during processing, andmay include other layers that have been fabricated thereupon. Both waferand substrate include doped and undoped semiconductors, epitaxialsemiconductor layers supported by a base semiconductor or insulator, aswell as other semiconductor structures well known to one skilled in theart. The term conductor is understood to include semiconductors, and theterm insulator or dielectric is defined to include any material that isless electrically conductive than the materials referred to asconductors.

[0040] The substrate 10 has a pad oxide layer 12 deposited thereon. Asused herein, the term deposited is used broadly to mean layers which arenot only deposited in the traditional sense, but layers of materialwhich are grown or in any other manner caused to be formed. A protectivelayer 14 is deposited on top of the pad oxide layer 12 to act as abuffer during subsequent etch steps and other processing. In oneembodiment, the protective layer 14 is polysilicon. In one embodiment,the protective layer 14 is a nitride material. In another embodiment,the protective layer 14 is a polysilicon layer that is covered with anitride material. The specific combination is selected depending uponprocess integration choices.

[0041] A mask 16 is formed and patterned upon the protective layer 14.In one embodiment, the mask 16 is a photoresist material that is spunon, exposed, cured, and patterned. In another embodiment, the mask 16 isa hard mask material such as a nitride or oxide. The area protected bythe mask 16 defines what will become an active area in a partialsilicon-on-insulator (SOI) structure.

[0042]FIG. 2 illustrates an embodiment after an etch process that hasexposed the regions unprotected by the mask 16. In the etch process, theprotective layer 14 and the pad oxide layer 12 have also been patterned,and a recess 18 has been formed with a recess first bottom 20 and arecess first wall 22.

[0043]FIG. 3 illustrates the structure depicted in FIG. 2 after furtherprocessing in which the mask 16 has been removed and a nitride film 24has been grown onto the exposed semiconductive material of the substrate10. In one embodiment, the exposed semiconductive material of thesubstrate 10 is exposed silicon. The nitride film 24 is depicted ascovering the recess first bottom 20 and the recess first wall 22. Thenitride film 24 may be grown by known processes under conditions thatdeposit only upon semiconductive material such as exposed silicon. Onesuch process is remote-plasma nitridation (RPN). In RPN, anitride-bearing plasma is struck, remote from substrate 10, but withinthe deposition tool, and the nitride-bearing plasma is carried byconvective force toward the substrate 10. In one embodiment, an RPNprocess is carried out in a time range from about 10 seconds to about 10minutes. In another embodiment, an RPN process is carried out in a timerange from about 1 minute to about 3 minutes. Another process that maybe used to form the nitride film 24 is rapid thermal nitridation (RTN).Such processing is also known in the art.

[0044] Alternative to the formation of a nitride film 24, an oxide filmmay be formed, either by remote-plasma oxidation (RPO) or by rapidthermal oxidation (RTO). Similarly, a combination of an oxide and anitride is formed according to an embodiment as set forth herein. In oneembodiment, the placement of the oxide precedes the placement of thenitride, or visa versa. Similarly, an oxynitride film is formed in theplace of the nitride film 24 according to an alternative embodiment. Theprocess is carried out by either a remote plasma process or a rapidthermal process. Although not limiting the embodiments disclosed, forconvenience throughout the remainder of the disclosure, the film 24 isreferred to a the nitride film 24.

[0045]FIG. 4 illustrates processing of the substrate 10 in which an etchhas formed a recess second bottom 26 below the level of the recess firstbottom 20. The recess first bottom 20 now appears as a substrate ledgestructure. Because of the presence of the nitride film 24, the recessfirst wall 22 is protected, and a recess second wall 28 has been formedthat is approximately coplanar with the lateral extremity of the nitridefilm 24. In one embodiment, an anisotropic etch, such as a reactive ionetch, is used such that the nitride film 24 is left standing upon theledge of what is left of the recess first bottom 20.

[0046] For a 0.25-micron critical-dimension (CD or minimum feature)process, the remnant of the nitride film 24 has a height in a range fromabout 0.1 microns to about 0.15 microns. In this dimension, the distancefrom the remnant of the recess first bottom 20 to the recess secondbottom 26 is in a range from about 0.1 microns to about 0.3 microns.Alternatively, for a 0.15-micron critical-dimension (CD or minimumfeature) process, the remnant of the nitride film 24 has a height, H, ina range from about 0.07 microns to about 0.12 microns. In thisdimension, the distance from the remnant of the recess first bottom 20to the recess second bottom 26 is in a range from about 0.08 microns toabout 0.2 microns.

[0047] At the level of the recess second bottom 26, a deep implantationregion 30 is formed. In one embodiment, the deep implantation region 30is made of materials that are substantially identical to the bulksemiconductive material in the substrate 10. Implantation is carried outat an energy level that achieves self-interstitial implantation, andthat causes the implantation region 30 to become amorphous enough tohave an etch responsiveness that is different from the bulksemiconductive material in the substrate 10. In one embodiment,implantation conditions use a silicon source that is implanted to amonocrystalline-to-self interstitial ratio of about 3:1. By “siliconsource” it is meant that silicon or another Group IV element is used, ora combination such as silicon and germanium. In one embodiment, theimplanted concentration is from about 1E14 atoms/cm² to about 5E15atoms/cm² at process conditions of ambient temperature (20 C to about 30C) and an implantation energy from about 20 KeV to about 30 KeV. In oneembodiment, a silicon source that is substantially equivalent to thesilicon chemistry of the bulk of the semiconductive substrate 10, isimplanted to a concentration of about 1E15 atoms/cm² and processconditions are about 25 C and an implantation energy of about 25 KeV.

[0048] After the deep implantation, an etch recipe is used in subsequentprocessing that is selective to the amorphous material of theimplantation region 30 and to the nitride film 24, but the etch reciperemoves bulk semiconductive material in the substrate 10. In oneembodiment, the etch recipe is a wet tetramethyl ammonium hydroxide(TMAH) etch as is known in the art. In another embodiment, the wet etchuses a potassium hydroxide (KOH) etch chemistry that is known in theart. The TMAH etch chemistry is desirable because it is selective suchthat it etches the bulk silicon of the substrate 10, but does notsubstantially etch the nitride film 24 or the implantation region 30. Inone embodiment, the selectivity is in a range from about 5:1 to about20:1. In another embodiment, the selectivity is about 10:1. Theisotropic etch may also be combined with an anisotropic etch, eitherbefore or after the isotropic etch. By using both an isotropic and ananisotropic etch, both the downward etching and the undercutting of thenitride film 24 may be varied to suit particular applications.

[0049] Various wet TMAH etch recipes are known that are selective toamorphous silicon and to nitride films (or oxide films, or oxynitridefilms), and that isotropically etch bulk monocrystalline silicon alongcrystallographic planes. FIG. 5 illustrates the results of a TMAH etchthat has formed a lateral cavity 34 that has undercut what will becomethe active area 32. By this undercutting etch, the active area 32 hasbeen mostly isolated from the bulk semiconductive material in thesubstrate 10, at the level of the ledge that is formed at the recessfirst bottom 20.

[0050] Under the etch conditions, and due to the scale of the lateralcavity 34, a distinctive contour may appear therein. The TMAH etch hasan effect along crystallographic planes such that a faceted contour mayappear within the lateral cavity 34. It can be seen that facetedsurfaces 36, 38, 40, and 42 are illustrated on one side. However, theseare depicted in arbitrary shape, angle and size for illustrativepurposes, and the specific shapes, angles, and sizes of the facetedsurfaces will depend upon the crystallographic orientation of the bulksemiconductive material in the substrate 10 and upon the specific etchrecipe and conditions, among other factors. According to the specificetch conditions, a photomicrographic view of the lateral cavity 34depicts substended crystallographic planes of bulk semiconductivematerial in the substrate 10 that have been exposed by the TMAH etch.

[0051] After formation of the lateral cavity 34, the implantation region30 is treated to form an annealed implantation region 44 as illustratedin FIG. 6. The annealed implantation region 44 has been returned tosubstantially the same semiconductive quality as the bulk semiconductivematerial in the substrate 10 by substantially repairing themonocrystalline lattice in what was the deep implantation region 30(FIG. 5). The conditions for annealing are known in the art, and dependupon the depth of the deep implantation region 30, the available thermalbudget of the process, and other factors.

[0052]FIG. 7 illustrates further processing according to an embodiment.In one embodiment, the exposed surface of the active area 32 and thebulk semiconductive material of the substrate 10 is oxidized. Knownthermal oxidation techniques are used. The oxidation 46 consumes silicondownward into the substrate 10, sideways into the faceted surfaces 36,38, 40, and 42 (FIG. 6), and upward into the bottom of the active area32. The oxidation 46 is depicted as following the previously exposedcontours of the recess second bottom 26 and the faceted surfaces 36, 38,40, and 42 within the lateral cavity 34, but the exact shape depicted isfor illustrative purposes and will vary, depending upon specific processconditions. The oxidation process, which may be referred to as aminifield oxidation, is precisely controlled to regulate the amount ofsubstrate material that is consumed.

[0053] According to an embodiment, the residue of the nitride film (FIG.6) is removed after forming the oxidation 46. Thereby, the originaldimension of the recess first wall 22 (FIG. 7) is substantiallyretained. In one photolithographic process, such as a 0.25-micronprocess, the dimensions are about 0.1 microns from the recess first wall22 to the lateral border 48 of the substrate stem 50 that remains. Inanother photolithographic process, such as a 0.15-micron process, thedimensions are about 0.07 microns (not pictured) from the recess firstwall 22 to the lateral border 48 of the silicon stem 50 that remains tothis stage of processing.

[0054] It is also depicted in FIG. 7, that the protective layer 14 hasremained while the nitride film 24 has been removed. This embodimentoccurs where the protective layer 14 is chemically different from thenitride film 24, such as a polysilicon protective layer 14. In anotherembodiment, where the protective layer 14 is a nitride material, it isremoved with the nitride film 24 after the minifield oxidation.

[0055] As mentioned for a given photolithographic process, the amount ofthe substrate 10 that is consumed sideways in the lateral cavity 34, forexample, is approximately 0.1 micron on each side of the active area 32,beginning at the recess first wall 22 and ending at the lateral border48 of the stem 50. That oxidation process leaves the stem 50 thatpartially isolates the substrate portion that will become the activearea 32 that is formed above a ledge, at the recess first bottom 20, inrelation to the bulk of the substrate 10. In this embodiment, the stem50 is on the order of 0.05 microns by 0.05 microns. Oxidation time willdepend upon the area of the partially isolated structure of the activearea 32 and the other parameters. In one embodiment, oxidationparameters include a processing temperature from about 850 C to about1,100 C. The ambient is with wet or dry oxygen (O₂), and atmosphericpressure or higher. In one example, a temperature of about 850 C and awet oxygen ambient is applied at about 1 atmosphere and for a sufficienttime to allow about 0.1 micron horizontal oxidation under the activearea 32, and about 0.1 micron vertical oxidation upwardly into theactive area 32. High pressure may be used to reduce the time requiredfor oxidation and to reduce the amount of oxide that forms behind thenitride film 24 (FIG. 5). High pressure includes atmospheric pressure,up to about 2 atmospheres and higher. After the thermal oxidationprocess, an oxide spacer 52 is formed by a blanket oxide deposition,such as by the decomposition of tetraethyl ortho silicate (TEOS),followed by a spacer etch as illustrated in FIG. 7.

[0056]FIG. 8 illustrates another embodiment, wherein the oxidationprocess is carried out under minimal conditions. The minimal oxidationrelates to a lowered workpiece stress in the lateral cavity 34. Anoxidation 46 is formed that leaves the lateral cavity 34 mostly void.The oxidation 46 consumes silicon downward into the substrate 10,sideways into the faceted surfaces 36, 38, 40, and 42 (FIG. 6), andupward into bottom of the active area 32. In one photolithographicprocess, such as a 0.25-micron process, the dimensions are about 0.03microns growth of oxidation 46 within the lateral cavity 34 to thelateral border 48 of the substrate stem 50 that remains. In anotherphotolithographic process, such as a 0.15-micron process, the dimensionsare about 0.01 microns (not pictured) within the lateral cavity 34 tothe lateral border 48 of the silicon stem 50 that remains to this stageof processing.

[0057] It is also depicted in FIG. 8, that the protective layer 14 hasremained while the nitride film 24 has been removed. This embodimentoccurs where the protective layer 14 is chemically different from thenitride film 24, such as a polysilicon protective layer 14. In anotherembodiment, where the protective layer 14 is a nitride material, it isremoved with the nitride film.

[0058] As mentioned for one photolithographic process, the amount of thesubstrate 10 that is consumed sideways by the isotropic etch, forexample, is approximately 0.07 micron on each side of the active area32. That oxidation process leaves the stem 50 that connects thesubstrate that will become the active area 32 to the bulk of thesubstrate 10. In this embodiment, the stem 50 is on the order of about0.05 microns by 0.05 microns. Oxidation time will depend upon the areaof the partially isolated structure that forms the active area 32 andthe other parameters. In one embodiment, oxidation parameters include aprocessing temperature from about 850 C to about 1,100 C. The ambient iswith wet or dry oxygen (O₂), atmospheric pressure or higher. In oneexample, a temperature of about 850 C and a wet oxygen ambient isapplied for a sufficient time to allow about 0.03 micron horizontaloxidation under the active area 32, and about 0.01 micron verticaloxidation upwardly into the active area 32. High pressure may be used toreduce the time required for oxidation and to reduce the amount of oxidethat forms behind the nitride film 24 (FIG. 5). High pressure is definedas a pressure above ambient including a range from about 1 atmosphere toabout 2 atmospheres, and higher. After the thermal oxidation process, anoxide spacer 52 is formed by a blanket oxide deposition, such as by thedecomposition of TEOS, followed by a spacer etch as illustrated in FIG.8. According to this embodiment, the oxide spacer 52 is formed underlow-pressure chemical vapor deposition (CVD) conditions that cause thelateral cavity 34 to remain partially void. Although no particulartheory of deposition is required, it is the low pressure that may causelonger mean-free paths of depositing oxide spacer material that leaves apartially void lateral cavity 34.

[0059] In another embodiment illustrated in FIG. 8, an oxide spacer 52is blanket deposited by physical vapor deposition (PVD) under conditionsthat also cause the lateral cavity 34 to remain partially or totallyvoid, followed by a spacer etch. In this embodiment, substantially nominifield oxidation is carried out before the blanket deposition andspacer etch of the oxide spacer 52. Thereby, the lateral cavity 34retains its faceted surfaces 36, 38, 40, and 42 (depicted in FIG. 6).However, unless the isotropic etch is followed by a micro-atmospheric-or oxygen-excluding process, a thin native oxide film 46, representedherein by the oxidation 46 in FIG. 8, will be present over the facetedsurfaces 36, 38, 40, and 42 (depicted in FIG. 6). This native oxide film46 in some embodiments is substantially monatomic, or a few atomiclayers thick in a range from about 2 Angstrom to about 8 Angstrom.

[0060]FIG. 9 illustrates an embodiment that relates to an oxidation thathas a thickness intermediate to the previous two embodiments. In thisembodiment, a process is carried out that partially fills the lateralcavity 34 with oxide material. The extent of fill into the lateralcavity 34 of the oxidation 46 is more than the extent of fill for theembodiment depicted in FIG. 8, and less than the extent of fill for theembodiment depicted in FIG. 7. Dimensions achieved by this embodimentare intermediate to the dimensions that are achieved in the embodimentdepicted in FIGS. 8 and 7. In one embodiment, the amount of thesubstrate 10 that is consumed sideways, for example, is approximately0.06 micron on each side of the stem 50. That oxidation process leavesthe stem 50 that connects the substrate that will become the active area32 to the bulk of the substrate 10. In this embodiment, the stem 50 ison the order of 0.05 microns by 0.05 microns.

[0061] The thickness of the stem 50 is set forth herein as about 0.05micron for each given embodiment depicted in FIGS. 7, 8 and 9. Thisthickness is controllable by the extent of the lateral etch that formsthe lateral cavity 34, in concert with the degree of growth of theoxidation 46. It can be appreciated that other thicknesses of the stem50 can be achieved, by controlling these parameters. Table 1 illustratesvarious geometries based upon lateral etches for a 0.25 micronlithography. The first three embodiments are depicted in FIGS. 7, 9, and8, respectively. The fourth embodiment is an example of a native oxideoxidation 46, wherein after fabrication, the facets 36, 38, 40, and 42(FIG. 6) are visible by photomicrography. TABLE 1 0.25 Micron ProcessGeometries Void Depth, Example micron Oxide 46, micron Stem 50, micron 10 0.1 .05 2 .03 .07 .05 3 .07 .03 .05 4 .0995 .0005 .05 5 .035 .06 .06 6.065 .03 .06 7 .0945 .0005 .06 8 0 .09 .07 9 .03 .06 .07 10 .06 .03 .0711 .0895 .0005 .07

[0062] Table 2 illustrates various geometries based upon varied lateraletches for a 0.15 micron geometry. TABLE 2 0.15 Micron ProcessGeometries Void Depth, Example micron Oxide 46, micron Stem 50, micron 10 0.06 .03 2 .02 .04 .03 3 .04 .02 .03 4 .0595 .0005 .03 5 0 .055 .04 6.015 .04 .04 7 .025 .03 .04 8 0 .05 .05 9 .02 .03 .05 10 .03 .02 .05 11.0495 .0005 .05

[0063]FIGS. 10 and 11 illustrate further processing according to anembodiment taken from the structure depicted in FIG. 9 by way ofnon-limiting example. FIG. 10 depicts structures constructed with theundercut that formed the lateral cavity 34. In FIG. 10, a larger portionof the substrate 10 is illustrated so that adjacent partially isolatedstructures of active areas 32 may be seen. The partially isolated activeareas 32 are separated by the recess 18 that, in this embodiment, actsas a shallow trench isolation (STI) trench. According to an embodiment,the recess 18 is filled with a material such as oxide by a known processsuch as a high-density plasma (HDP) technique. In one embodiment, thesubstrate 10 is blanket HDP deposited with an oxide fill 54 depositionwhich blankets the substrate 10 and which fills the recess 18.Thereafter, the oxide fill 54 is etched back by a process that stops onthe protective layer 14 if it is present as a polysilicon material.Where the protective layer 14 is present as a polysilicon material,overetching of the oxide fill 54 may occur. The etching back process iscarried out according to process needs, such as by chemical-mechanicalpolishing (CMP), mechanical polishing (MP), chemical etchback, andothers.

[0064] Another embodiment occurs where no protective layer 14 hasremained during processing to this extent of the process. For example,where the protective layer 14 is a nitride material, it is removedsimultaneously with the remnant of the nitride film 24 (FIG. 6).According to this embodiment, an oxide fill 54 is a doped or undopedmaterial that shows a distinctive etch responsiveness in comparison tothe pad oxide layer 12, such that the pad oxide layer 12 acts as theetch stop.

[0065] As depicted in FIG. 10, the material filling the recess 18 isetched or planarized so that the top surface 56 of the oxide fill 54 isapproximately even with the top surface of the pad oxide layer 12. Wherethe protective layer 14 is present such as a polysilicon material, theremnants of the protective layer 14 is stripped in a manner so as not todamage the remnants of the pad oxide layer 12. In one embodiment, theremnant of the pad oxide layer 12 is used as a gate oxide for thefabrication of active devices above the active area 32.

[0066] Total isolation between devices on the active areas 32 can be asmuch as 0.65 microns (0.2 microns of the oxide fill 54, plus 0.25microns of the active are 32, plus 0.2 microns of the oxide fill 54) fora given 0.25-micron lithography. Furthermore, the field oxide regionsare comprised of both thermal oxide and deposited oxide so that theadvantages of each type of oxide can be gained.

[0067] The structure depicted in FIG. 10 is also depicted in FIG. 11 asa storage device, wherein two dynamic random access (DRAM) memory cellsare formed thereon. Active devices in the form of a digit line junction58 and storage node junctions 60 and 62 are formed in the partiallyisolated active area 32. A word line 64 overlays the active area 32. Thestorage node junctions 60 and 62 are in electrical contact withrespective capacitors 66 and 68 through polysilicon plugs 70. The digitline junction 58 is in electrical contact with a polysilicon plug 72.The polysilicon plug 72 is a contact that touches the active area 32.The polysilicon plug 72 is in further contact with a digit line 74through a metal plug 76.

[0068] A substrate 10 carrying a partially isolated active area 32provides a vehicle for the fabrication of a storage device such as aDRAM cell, or virtually any type of logic circuit that employs a MOSFET.

[0069] While the structure depicted in FIG. 11 illustrates one type ofdevice which might be fabricated upon the workpiece of the substrate 10and with the use of the partially isolated active area 32, those ofordinary skill in the art will recognize the advantages of fabricatingother types of devices according to various embodiments and theirequivalents. In particular, active devices formed in the partiallyisolated active area 32 will be substantially isolated from the bulk ofthe substrate 10.

[0070]FIG. 12 illustrates another process embodiment in which a deepimplantation region is first implanted into the substrate. In thisembodiment, the substrate 110 has a deep implantation region 130 thathas been blanket implanted to a depth that is qualitatively equivalentto the location of the deep implantation region 30 depicted in FIG. 4.In one embodiment, the deep implantation region 130 is made of materialsthat are identical to the bulk semiconductive material in the substrate110. At the level of the recess second bottom 26, a deep implantationregion 30 is formed. In one embodiment, the deep implantation region 30is made of materials that are substantially identical to the bulksemiconductive material in the substrate 10. Implantation is carried outat an energy level that achieves self-interstitial implantation, andthat causes the implantation region 30 to become amorphous enough tohave an etch responsiveness that is different from the bulksemiconductive material in the substrate 10. In one embodiment,implantation conditions use a silicon source that is implanted to amonocrystalline-to-self interstitial ratio of about 3:1. By “siliconsource” it is meant that silicon or another Group IV element is used, ora combination such as silicon and germanium. In one embodiment, theimplanted concentration is from about 5E14 atoms/cm² to about 5E15atoms/cm² at process conditions of ambient temperature (20 C to about 30C) and an implantation energy from about 20 KeV to about 30 KeV. In oneembodiment, a silicon source that is substantially equivalent to thesilicon chemistry of the bulk of the semiconductive substrate 10, isimplanted to a concentration of about 25E14 atoms/cm² and processconditions are about 25 C and an implantation energy of about 25 KeV.The vertical implantation profile is controlled to be narrow withrespect to the specific process geometry. In one embodiment, thevertical implantation profile has a height of about 0.05 microns whenmeasured upwardly, beginning at the level that will make up the recesssecond bottom 126 (see FIG. 15).

[0071] A pad oxide layer 112 is also deposited on the substrate 110, aswell as a protective layer 114 on top of the pad oxide layer 112 to actas a buffer during subsequent etch steps and other processing. In oneembodiment, the protective layer 114 is polysilicon. In one embodiment,the protective layer 114 is a nitride material. In another embodiment,the protective layer 114 is a polysilicon layer that is covered with anitride material. The specific combination is selected depending uponprocess integration choices.

[0072] A mask 116 is formed and patterned upon the protective layer 114.In one embodiment, the mask 116 is a photoresist material or a hard maskmaterial such as a nitride or oxide according to embodiments set forthherein. The area protected by the mask 116 defines what will become apartially isolated active area in a partial SOI structure.

[0073]FIG. 13 illustrates an embodiment after an etch process that hasexposed the regions unprotected by the mask 116. In the etch process,the protective layer 114 and the pad oxide layer 112 have also beenpatterned, and a recess 118 has been formed with a recess first bottom120 and a recess first wall 122.

[0074]FIG. 14 illustrates the structure depicted in FIG. 13 afterfurther processing in which the mask 116 has been removed and a nitridefilm 124 has been grown onto the exposed semiconductive material of thesubstrate 110. In one embodiment, the exposed semiconductive material ofthe substrate 110 is exposed silicon. The nitride film 124 is depictedas covering the recess first bottom 120 and the recess first wall 122.The nitride film 124 may be grown by known process under conditions thatdeposit only upon semiconductive material such as exposed silicon as setforth herein for the embodiments depicted in FIG. 3 such as RPN, RTN,RPO, and RTO.

[0075]FIG. 15 illustrates processing of the substrate 110 in which anetch has formed a recess second wall 128 and a recess second bottom 126below the level of the recess first bottom 120. Because of the presenceof the nitride film 124, the recess first wall 122 is protected, and therecess second wall 128 has been formed that is approximately coplanarwith the lateral extremity of the nitride film 124. In one embodiment,an anisotropic etch, such as a reactive ion etch, is used such that thenitride film 124 is left standing upon what is left of the recess firstbottom 120. For a 0.25-micron CD process, the remnant of the nitridefilm 124 has a height, H, in a range from about 0.1 micron to about 0.15microns. In this dimension, the distance from the remnant of the recessfirst bottom 120 to the recess second bottom 126 is in a range fromabout 0.1 micron to about 0.3 microns.

[0076] At the level of the recess second bottom 126, the deepimplantation region 130 is exposed. According to an embodiment, the deepimplantation region 130 acts as an etch stop. In one example, ananisotropic etch is carried out that has an etch recipe selective to thedeep implantation region 130.

[0077] In another embodiment, external process control is used to stopthe etch at the level of the deep implantation region 130. After theetch that either stops on the deep implantation region 130 by chemicalselectivity, or by external process control, an isotropic etch recipe isused in subsequent processing that is selective to the amorphousmaterial of the deep implantation region 130, but the etch reciperemoves bulk semiconductive material in the substrate 110. In oneembodiment, the etch recipe is a wet TMAH etch as set forth herein forother embodiments. In another embodiment, the wet etch uses a KOH etchchemistry as set forth herein for other embodiments. The isotropic etchmay also be combined with an anisotropic etch, either before or afterthe isotropic etch. By using both an isotropic and an anisotropic etch,both the downward etching and the undercutting of the nitride film 124may be varied to suit particular applications.

[0078] Various wet TMAH etch recipes are known that are selective toamorphous silicon and to nitride films, and that isotropically etch bulkmonocrystalline silicon along crystallographic planes. FIG. 16illustrates the results of a TMAH etch that has formed a lateral cavity134 that has undercut the active area 132. By this undercutting etch,the active area 132 has been mostly separated from the bulksemiconductive material in the substrate 110 and substantially noetching through the deep implantation region 130 has occurred.

[0079] Under the etch conditions, and due to the scale of the lateralcavity 134, a distinctive contour may appear therein. The TMAH etch hasan effect along crystallographic planes such that a faceted contour mayappear within the lateral cavity 134. It can be seen that facetedsurfaces 136, 138, 140, and 142 are illustrated. However, these aredepicted in arbitrary shape, angle and size for illustrative purposes,and the specific shapes, angles, and sizes of the faceted surfaces willdepend upon the crystallographic orientation of the bulk semiconductivematerial in the substrate 110 and the specific etch conditions.According to the specific etch conditions, a photomicrographic view ofthe lateral cavity 134 will depict substended crystallographic planes ofbulk semiconductive material in the substrate 110 that have been exposedby the TMAH etch.

[0080] After formation of the lateral cavity 134, the deep implantationregion 130 is treated to form an annealed deep implantation region 144as illustrated in FIG. 17. Particularly at free surfaces, the annealeddeep implantation region 144 has been return to substantially the samesemiconductive quality as the bulk semiconductive material in thesubstrate 110 by repairing at least some of the monocrystalline latticein what was the deep implantation region 130 (FIG. 16). Furtherprocessing, including oxidation, oxide spacer formation, STI oxide fillprocessing, planarization, and device construction, among otherprocesses are carried out as set forth in embodiments in thisdisclosure.

[0081]FIG. 18 illustrates another embodiment in which two implantationregions are first implanted into the substrate. In one embodiment, thesubstrate 210 has a deep implantation region 230 that has been firstblanket implanted to a qualitative depth that is equivalent to thelocation of the deep implantation region 30 depicted in FIG. 4, or thedeep implantation region 130 depicted in FIG. 14. A shallow implantationregion 278 is second blanket implanted into the substrate 210. Theshallow implantation region 278 is implanted to a qualitative depth thatis equivalent to the location of the recess first bottom 20 depicted inFIG. 4, or the recess first bottom 120 depicted in FIG. 14. As in otherembodiments set forth herein, the deep implantation region 230 and theshallow implantation region 278 are implanted with materials that aresubstantially identical to the bulk semiconductive material in thesubstrate 210. Implantation is carried out at an energy level thatachieves self-interstitial implantation, and that causes theimplantation regions 230 and 278 to become amorphous enough to have anetch responsiveness that is different from the bulk semiconductivematerial in the substrate 210. The achievement of the implantationregions 230 and 278 is done according to processing conditions known inthe art, and as set forth herein. The implantation profiles arecontrolled to be narrow with respect to the specific process geometry.In one embodiment, the implantation profiles each have a height of about0.05 microns.

[0082] A pad oxide layer 212 is also deposited on the substrate 210, aswell as a protective layer 214 on top of the pad oxide layer 212 to actas a buffer during subsequent etch steps and other processing. In oneembodiment, the protective layer 214 is polysilicon. In one embodiment,the protective layer 214 is a nitride material. In another embodiment,the protective layer 214 is a polysilicon layer that is covered with anitride material. The specific combination is selected depending uponprocess integration choices.

[0083] A mask 216 is formed and patterned upon the protective layer 214.As set forth herein for other embodiments, the mask 216 is either aphotoresist material or a hard-mask material such as a nitride or oxide.The area protected by the mask 116 defines what will become a partiallyisolated active area in a partial SOI structure.

[0084]FIG. 19 illustrates an embodiment after an etch process that hasexposed the regions unprotected by the mask 216. In the etch process,the protective layer 214 and the pad oxide layer 212 have also beenpatterned, and a recess 218 has been formed with a recess first bottom220 and a recess first wall 222. It is noted that the first etch hasalso stopped at or below the level of the shallow implantation region278.

[0085]FIG. 20 illustrates the structure depicted in FIG. 19 afterfurther processing in which the mask 216 has been removed and a nitridefilm 224 has been grown onto the exposed semiconductive material of thesubstrate 210. In one embodiment, the exposed semiconductive material ofthe substrate 210 is exposed silicon. The nitride film 224 is depictedas covering the recess first bottom 220 and the recess first wall 222.The nitride film 224 may be grown by known process under conditions thatdeposit only upon semiconductive material such as exposed silicon as setforth herein for the embodiments depicted in FIG. 3 and FIG. 14. Thenitride film 224 may be grown by known process under conditions thatdeposit only upon semiconductive material such as exposed silicon as setforth herein for the embodiments depicted in FIG. 3 such as RPN, RTN,RPO, and RTO.

[0086]FIG. 21 illustrates processing of the substrate 210 in which anetch has formed a recess second wall 228 and a recess second bottom 226below the level of the recess first bottom 220. Because of the presenceof the nitride film 224, the recess first wall 222 is protected, and therecess second wall 228 has been formed that is approximately coplanarwith the lateral extremity of the nitride film 224. In one embodiment,an anisotropic etch, such as a reactive ion etch, is used such that thenitride film 224 is left standing upon what is left of the recess firstbottom 220. For a 0.25-micron CD process, the remnant of the nitridefilm 224 has a height, H, in a range from about 0.1 microns to about0.15 microns. In this dimension, the distance from the remnant of therecess first bottom 220 to the recess second bottom 226 is in a rangefrom about 0.1 microns to about 0.3 microns. According to an embodiment,the deep implantation region 230 acts as an etch stop. In one example,an anisotropic etch is carried out that has an etch recipe selective tothe deep implantation region 230.

[0087]FIG. 22 illustrates further processing according to an embodiment.After the etch that either stops on the deep implantation region 230 bychemical selectivity, or by external control, an isotropic etch recipeis used in subsequent processing that is selective to the amorphousmaterial of the shallow implantation region 278 and the deepimplantation region 230. The etch recipe removes bulk semiconductivematerial in the substrate 110 that lies between the shallow implantationregion 278 and the deep implantation region 230. In this embodiment, theformation of a lateral cavity 234 is restricted by the presence of theshallow implantation region 278 above, and the deep implantation region230 below. Accordingly, the height 280 of the lateral cavity 234 iscontrollable, subject to process restrictions such as the depths of therespective the shallow- and deep implantation regions 278 and 230 andtheir spacing apart one from the other. In one embodiment, the height280 is in a range from about 0.01 microns to about 0.1 microns. Inanother embodiment, the height 280 is about 0.02 microns. Thisembodiment is useful wherein a voided lateral cavity 234 will have adielectric constant essentially that of air because any oxidation orsubsequent fill of the recess 218 may not penetrate into the lateralcavity 234.

[0088] In one embodiment, the etch recipe for forming the lateral cavity234 is a wet TMAH etch as set forth herein for other embodiments. Inanother embodiment, the wet etch uses a KOH etch chemistry as set forthherein for other embodiments. The isotropic etch may also be combinedwith an anisotropic etch, either before or after the isotropic etch.

[0089]FIG. 22 illustrates the results of a TMAH etch that has formed thelateral cavity 234 that has undercut the active area 232. By thisundercutting etch, the active area 232 has been mostly separated fromthe bulk semiconductive material in the substrate 210.

[0090] Under the etch conditions, and due to the scale of the lateralcavity 234, a distinctive contour may appear therein. The TMAH etch hasan effect along crystallographic planes such that a faceted contour mayappear within the lateral cavity 234 as discussed for embodimentsdepicted in FIGS. 5 and 16. As set forth for other embodiments, thespecific shapes, angles, and sizes of the faceted surfaces will dependupon the crystallographic orientation of the bulk semiconductivematerial in the substrate 210. According to the specific etchconditions, a photomicrographic view of the lateral cavity 234 willdepict substended crystallographic planes of bulk semiconductivematerial in the substrate 210 that have been exposed by the TMAH etch.

[0091] After formation of the lateral cavity 234, the implantationregions 278 and 230 are treated by a process such as solid-phase epitaxyto form annealed implantation regions 282 and 244, respectively, asillustrated in FIG. 23. Particularly at the free surfaces, the annealedimplantation regions 282 and 244 have been returned to substantially thesame semiconductive quality as the bulk semiconductive material in thesubstrate 110 by repairing the monocrystalline lattice in what was theimplantation region 278 and 230 (FIG. 22). In one embodiment, althoughsome portions of the implantation regions 278 and 230 (FIG. 22) may nottotally return to substantially the same semiconductive quality as thebulk semiconductive material in the substrate 210 and in the active area232, the depth 224 of the active area 232 (also measured by the height,H, of the nitride film) may be controlled such that the amorphousportions, if any, that remain will be significantly far from the finalchannel and junctions of the active area 232 such that they areoperative. Further processing, including minifield oxidation, oxidespacer formation, STI oxide fill processing, planarization, and deviceconstruction, among other processes are carried out as set forth inembodiments in this disclosure. In one embodiment, the minifieldoxidation consumes significant remaining implantation regions 282 and244.

[0092] To one of ordinary skill in the art, it now becomes clear thatother processing variations are possible. For example (referring toFIGS. 2 and 4 as a guide), the deep implantation region 30 may be firstformed after the first etch by implanting through the recess firstbottom 20 to what will become the level of the recess second bottom 26.In this example, the deep implantation region 30 may be formed in areactive ion etch (RIE) chamber that also carries out the second etch,and the conditions can proceed after the first etch and growth of thenitride film 24 by an ion implantation to form the deep implantationregion 30 through the first bottom, and a second etch that stops on thedeep implantation region 30.

[0093] The processes and structures that are achieve in the variousembodiments are inventively applicable to a variety of devices andapparatuses. Preferred systems may be made by process embodiments, orthat include an embodiment or embodiments of the structure. For example,a chip package may contain a partially isolated structure such as anactive area set forth in this disclosure. In one embodiment, an array ofactive areas is included such as a line of sense amplifiers that use theactive areas, or a 2-dimensional array of storage devices such as a DRAMarray. In another embodiment, the partially isolated structure is partof an electrical device that includes the semiconductor substrate in achip package and the chip package is part of a memory module or part ofa chipset. In another embodiment, the memory module is part of a dynamicrandom access memory module that is inserted into a host such as amotherboard or a digital computer. In another embodiment, preferredsystems may be made that include the partially isolated structure. Forexample, a chip package may contain a substrate such as one set forth inthis disclosure. In another embodiment, the partially isolated structureis part of an electrical device that includes the semiconductorsubstrate in a chip package and the chip package is part of a memorymodule or part of a chipset. In another embodiment, the memory module ispart of a dynamic random access memory module that is inserted into ahost such as a motherboard or a digital computer. In another embodiment,the partially isolated structure is part of an electronic system. Inanother embodiment, the partially isolated structure is fabricated witha floating gate. In another embodiment, the partially isolated structureis fabricated with a floating gate that is part of a flash memory devicethat in turn is part of a chipset such as a basic input-output system(BIOS) for an electrical device.

[0094] In another embodiment, preferred systems may be made that includethe partially isolated structure. With reference to FIG. 24, asemiconductor die 2410 may be produced from a silicon wafer 2400 thatmay contain the partially isolated active area structures 32, 132, and232 respectively, such as are depicted in FIGS. 7, 8, and 9. A die 2410is an individual pattern, typically rectangular, on a substrate such assubstrate 10, substrate 110, and substrate 210, that contains circuitryto perform a specific function. A semiconductor wafer 2400 willtypically contain a repeated pattern of such dies 2410 containing thesame functionality. Die 2410 may further contain additional circuitry toextend to such complex devices as a monolithic processor with multiplefunctionality. Die 2410 is typically packaged in a protective casing(not shown) with leads extending therefrom (not shown) providing accessto the circuitry of the die 2410 for unilateral or bilateralcommunication and control. In one embodiment, die 2410 is incased in ahost such as a chip package (not shown) such as a chip-scale package(CSP).

[0095] As shown in FIG. 25, two or more dies 2410 at least one of whichcontains at least one partially isolated structure such as is depictedin FIGS. 7, 8, and 9, in accordance with various embodiments may becombined, with or without protective casing, into a host such as acircuit module 2500 to enhance or extend the functionality of anindividual die 2410. Circuit module 2500 may be a combination of dies2410 representing a variety of functions, or a combination of dies 2410containing the same functionality. Some examples of a circuit module2500 include memory modules, device drivers, power modules,communication modems, processor modules and application-specific modulesand may include multi-layer, multi-chip modules. Circuit module 2500 maybe a sub-component of a variety of electronic systems, such as a clock,a television, a cell phone, a personal computer, an automobile, anindustrial control system, an aircraft, a hand-held, and others. Circuitmodule 2500 will have a communication and control. In anotherembodiment, circuit module 2500 has a storage device such as is depictedin FIG. 11.

[0096]FIG. 26 shows one embodiment of a circuit module as memory module2600 containing a structure for the inventive partially isolatedstructure such as are depicted in FIGS. 7, 8, and 9, or the storagedevice as is depicted in FIG. 11. Memory module 2600 is a host for thatgenerally depicts a Single In-line Memory Module (SIMM) or Dual In-lineMemory Module (DIMM). A SIMM or DIMM may generally be a printed circuitboard (PCB) or other support containing a series of memory devices.While a SIMM will have a single in-line set of contacts or leads, a DIMMwill have a set of leads on each side of the support with each setrepresenting separate I/O signals. Memory module 2600 contains multiplememory devices 2610 contained on support 2615, the number depending uponthe desired bus width and the desire for parity. Memory module 2600 maycontain memory devices 2610 on both sides of support 2615. Memory module2600 accepts a command signal from an external controller (not shown) ona command link 2620 and provides for data input and data output on datalinks 2630. The command link 2620 and data links 2630 are connected toleads 2640 extending from the support 2615. Leads 2640 are shown forconceptual purposes and are not limited to the positions shown in FIG.26.

[0097]FIG. 27 shows another host type such as an electronic system 2700containing one or more circuit modules 2500 as described abovecontaining at least one of the inventive partially isolated structuresor data storage devices. Electronic system 2700 generally contains auser interface 2710. User interface 2710 provides a user of theelectronic system 2700 with some form of control or observation of theresults of the electronic system 2700. Some examples of user interface2710 include the keyboard, pointing device, monitor and printer of apersonal computer; the tuning dial, display and speakers of a radio; theignition switch of gas pedal of an automobile; and the card reader,keypad, display and currency dispenser of an automated teller machine.User interface 2710 may further describe access ports provided toelectronic system 2700. Access ports are used to connect an electronicsystem to the more tangible user interface components previouslyexemplified. One or more of the circuit modules 2500 may be a processorproviding some form of manipulation, control or direction of inputs fromor outputs to user interface 2710, or of other information eitherpreprogrammed into, or otherwise provided to, electronic system 2700. Aswill be apparent from the lists of examples previously given, electronicsystem 2700 will often contain certain mechanical components (not shown)in addition to the circuit modules 2500 and user interface 2710. It willbe appreciated that the one or more circuit modules 2500 in electronicsystem 2700 can be replaced by a single integrated circuit. Furthermore,electronic system 2700 may be a sub-component of a larger electronicsystem.

[0098]FIG. 28 shows one embodiment of an electrical device at a systemlevel. The electronic system depicted in FIG. 28 is a memory system2800. Memory system 2800 acts as a higher-level host that contains oneor more memory modules 2600 as described above including at least one ofthe partially isolated structure or the data storage device such as setforth herein in accordance with the present invention and a memorycontroller 2810 that may also include circuitry for the inventivepartially isolated structure or the data storage device. Memorycontroller 2810 provides and controls a bidirectional interface betweenmemory system 2800 and an external system bus 2820. Memory system 2800accepts a command signal from the external system bus 2820 and relays itto the one or more memory modules 2600 on a command link 2830. Memorysystem 2800 provides for data input and data output between the one ormore memory modules 2600 and external system bus 2820 on data links2840.

[0099]FIG. 29 shows a further embodiment of an electronic system as acomputer system 2900. Computer system 2900 contains a processor 2910 anda memory system 2800 housed in a computer unit 2915. Computer system2900 is but one example of an electronic system containing anotherelectronic system, i.e. memory system 2600, as a sub-component. Thecomputer system 2900 may contain an input/output (I/O) circuit 2920 thatis coupled to the processor 2910 and the memory system 2600. Computersystem 2900 optionally contains user interface components that arecoupled to the I/O circuit 2920. In accordance with the presentinvention a plurality partially isolated structures or data storagedevices may each be coupled to one of a plurality of I/O pads or pins2930 of the I/O circuit 2920. The I/O circuit 2920 may then be coupled amonitor 2940, a printer 2950, a bulk storage device 2960, a keyboard2970 and a pointing device 2980. It will be appreciated that othercomponents are often associated with computer system 9400 such asmodems, device driver cards, additional storage devices, etc. It willfurther be appreciated that the processor 2910, memory system 2600, I/Ocircuit 2920 and partially isolated structures or data storage devicesof computer system 2900 can be incorporated on a single integratedcircuit. Such single package processing units reduce the communicationtime between the processor 2910 and the memory system 2900.

CONCLUSION

[0100] Thus has been shown a partially isolated active area and aprocess of fabricating the partially isolated active area that uses atleast a deep implantation region to facilitate an etch that forms alateral cavity. Embodiments of the present invention relate to processesthat facilitate the partial isolation of the active area and varyingdegrees of oxidation if present in the lateral cavity. The partialisolation is carried out by an etch that is selective to an deepimplantation region. The deep implantation region has been temporarilymade amorphous, and a silicon ledge forms above the amorphous material.The process solves the problem of achieving an etch differential qualityat the bottom of a trench that was carried out by other methods such asan extra deposition. The process also results in various degrees ofpartial isolation, depending upon the extent of a minifield oxidationoperation, if it is present. Where there is a native oxide film in thelateral recess, a faceted surface remains as a result of the specificetch conditions.

[0101] A structure is also achieved that includes a faceted lateralcavity in one embodiment. The faceted lateral cavity acts to partiallyisolate the active area from the bulk of the substrate.

[0102] While the present invention has been described in connection witha preferred embodiment thereof, those of ordinary skill in the art willrecognize that many modifications and variations may be employed. Forexample, the sample dimensions and process parameters disclosed hereinmay be varied and are disclosed for the purpose of illustration and notlimitation. The foregoing disclosure and the following claims areintended to cover all such modifications and variations.

What is claimed is:
 1. An electrical device comprising: a semiconductivesubstrate; a recess disposed in the substrate, wherein the recessincludes a recess wall and a recess bottom; a lateral cavity disposedbelow the recess wall and at the recess bottom, wherein the lateralcavity has a depth in a range from about 0.12 microns to about 0.02microns and wherein the lateral cavity includes a faceted surface thatfollows crystallographic planes in the semiconductive substrate; and anactive area above the lateral cavity, wherein the active area ispartially isolated from the substrate by the lateral cavity.
 2. Theelectrical device according to claim 1, further including: a chippackage, wherein the substrate is disposed in the chip package.
 3. Theelectrical device according to claim 1, further including: a chippackage, wherein the substrate is disposed in the chip package; and ahost, wherein the chip package is disposed in the host.
 4. Theelectrical device according to claim 1, further including: a chippackage, wherein the substrate is disposed in the chip package; and ahost, wherein the chip package is disposed in the host, wherein the hostincludes a memory module.
 5. The electrical device according to claim 1further including: a chip package, wherein the substrate is disposed inthe chip package; and a host, wherein the chip package is disposed inthe host, wherein the host includes a memory module; and an electronicsystem, wherein the memory module is disposed in the electronic system.6. The electrical device according to claim 1, further including: a chippackage, wherein the substrate is disposed in the chip package; a host,wherein the chip package is disposed in the host, wherein the hostincludes a dynamic random access memory module; and an electronicsystem, wherein the dynamic random access memory module is disposed inthe electronic system.
 7. The electrical device according to claim 1,further including: a chip package, wherein the substrate is disposed inthe chip package; a host, wherein the chip package is disposed in thehost; and an electronic system, wherein the host is disposed in theelectronic system.
 8. A computer system, comprising: a processor; amemory system coupled to the processor; an input/output (I/O) circuitcoupled to the processor and the memory system; and a partially isolatedstructure disposed in the processor or the memory system, the partiallyisolated structure including: a semiconductive substrate; a recessdisposed in the substrate, wherein the recess includes a recess wall anda recess bottom; a lateral cavity disposed below the recess wall and atthe recess bottom, wherein the lateral cavity has a depth in a rangefrom about 0.12 microns to about 0.02 microns and wherein the lateralcavity includes a faceted surface that follows crystallographic planesin the semiconductive substrate; and an active area above the lateralcavity, wherein the active area is partially isolated from the substrateby the lateral cavity.
 9. The computer system according to claim 8,wherein the processor is disposed in a host selected from a clock, atelevision, a cell phone, a personal computer, an automobile, anindustrial control system, an aircraft, and a hand-held.
 10. Thecomputer system according to claim 8, wherein the memory system isdisposed in a host selected from a clock, a television, a cell phone, apersonal computer, an automobile, an industrial control system, anaircraft, and a hand-held.
 11. A storage device comprising: asemiconductive substrate; a recess disposed in the substrate, whereinthe recess includes a recess first wall and a recess second bottom; alateral cavity disposed below the recess first wall and at the recesssecond bottom, wherein the lateral cavity includes a faceted surfacethat follows crystallographic planes in the semiconductive substrate; anactive area above the lateral cavity, wherein the active area ispartially isolated from the substrate by the lateral cavity; a digitline junction and a storage node junction in the partially isolatedactive area; a word line, wherein the word line overlays the partiallyisolated active area; a polysilicon plug in electrical contact with thepartially isolated active area; a storage node in electrical contactwith the polysilicon plug; and a digit line coupled to the digit linejunction.
 12. The storage device of claim 11, wherein the lateral cavityhas a depth in a range from about 0.12 microns to about 0.02 microns.13. The storage device of claim 11, wherein the storage node junction ispart of a plurality of two storage node junctions, wherein thepolysilicon plug is part of a plurality of two polysilicon plugs, andwherein the storage node is part of a plurality of two storage nodes.14. The storage device of claim 11, further including: a chip package,wherein the substrate is disposed in the chip package.
 15. An articlecomprising: a semiconductive substrate; a recess disposed in thesubstrate, wherein the recess includes a recess wall and a recessbottom; a lateral cavity disposed below the recess wall and at therecess bottom, wherein the lateral cavity includes a faceted surfacethat follows crystallographic planes in the semiconductive substrate; anactive area above the lateral cavity, wherein the active area ispartially isolated from the substrate by the lateral cavity; and a deepimplantation region, wherein the deep implantation region extends fromthe lateral cavity and substantially continuously across and below theactive area.
 16. The article of claim 15, wherein the lateral cavity hasa depth in a range from about 0.12 microns to about 0.02 microns. 17.The article of claim 15, wherein the deep implantation region includesan implanted concentration in a range from about 5E14 atoms/cm² to about5E15 atoms/cm².
 18. The article of claim 15, further including: a chippackage, wherein the substrate is disposed in the chip package.
 19. Anarticle comprising: a semiconductive substrate; a recess disposed in thesubstrate, wherein the recess includes a recess wall and a recessbottom; a lateral cavity disposed below the recess wall and at therecess bottom, wherein the lateral cavity includes a faceted surfacethat follows crystallographic planes in the semiconductive substrate; anactive area above the lateral cavity, wherein the active area ispartially isolated from the substrate by the lateral cavity; a shallowimplantation region, wherein the shallow implantation region extendsfrom the recess wall and substantially continuously across and below theactive area; and a deep implantation region, wherein the deepimplantation region extends from the lateral cavity and substantiallycontinuously across and below the active area.
 20. The article of claim19, wherein the lateral cavity has a depth in a range from about 0.12microns to about 0.02 microns.
 21. The article of claim 19, wherein thedeep implantation region includes an implanted concentration in a rangefrom about 5E14 atoms/cm² to about 5E15 atoms/cm².
 22. The article ofclaim 19, further including: a chip package, wherein the substrate isdisposed in the chip package.
 23. An electrical device comprising: asemiconductive substrate; a recess disposed in the substrate, whereinthe recess includes a recess wall and a recess bottom; a lateral cavitydisposed below the recess wall and at the recess bottom, wherein thelateral cavity has a depth in a range from about 0.12 microns to about0.02 microns and wherein the lateral cavity includes a faceted surfacethat follows crystallographic planes in the semiconductive substrate;and an active area above the lateral cavity, wherein the active area ispartially isolated from the substrate by the lateral cavity, wherein thelateral cavity defines a portion of a stem which connects the substrateto the active area, and wherein the stem includes a thickness in a rangefrom about 0.05 micron to about 0.07 micron.
 24. The electrical deviceof claim 23, further including an oxide disposed in the lateral cavity,wherein the oxide includes a thickness in a range from about 0.0005micron to about 0.1 micron.
 25. The electrical device of claim 23,further including: a chip package, wherein the substrate is disposed inthe chip package.